1. Field of the Invention
The present invention relates to liquid crystal display devices for minimizing picture quality deterioration caused by signal distortion.
2. Description of the Related Art
Generally, a liquid crystal display device controls the light transmittance of a liquid crystal by use of electric fields, thereby displaying a picture.
FIG. 1 is a diagram representing a liquid crystal display device of the related art. Referring to FIG. 1, the related art liquid crystal display device includes a liquid crystal display panel 1; a plurality of data tape carrier packages (TCP) 8, which are connected between the liquid crystal display panel 1 and data printed circuit boards (PCB) 12; a plurality of gate TCPs 14A to 14D connected to another side of the liquid crystal display panel 1; data driver integrated circuits (IC) 10 mounted on each of the data TCPs 8; and gate drive ICs 16A to 16D mounted on each of the gate TCPs 14A to 14D.
The liquid crystal display panel 1 includes a lower substrate 2 where a thin film transistor array is formed together with various signal lines; an upper substrate 4 where a color filter array is formed; and a liquid crystal, which is injected between the lower substrate 2 and the upper substrate 4. The liquid crystal display panel 1 includes a picture display area 21, wherein the picture display area 21 includes liquid crystal cells that are defined by the crossing of the gate lines 20 and the data lines 18. Data pads extend from the data line 18, and gate pads extend from the gate line 20, in the outer area of the lower substrate 2 located at an outer part of the picture display area 21.
The data TCP 8 has the data drive IC 10 mounted on it and input pads 24 and output pads 25 electrically connected to the data driver IC 10. The input pads 24 of the data TCP 8 are electrically connected to the output pads 25 of a data PCB 12 through an anisotropic conductive film (hereinafter “ACF”), and the output pads 25 are electrically connected to the data pads on the lower substrate 2 through the ACF.
The data driver ICs 10 convert a digital pixel data signal into an analog pixel voltage signal and supply the analog pixel signal to the corresponding data line 18 on the liquid crystal display panel 1.
The gate TCP 14A to 14D respectively have gate driver ICs 16A to 16D mounted on them, a gate drive signal transmission line group 28, and the output pads formed to connected to the gate driver ICs 16A to 16D. The gate driver signal transmission line group 28 is electrically connected to the signal line group 26 on the lower substrate 2 through the ACF, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2 through the ACF.
The gate driver ICs 16A to 16D sequentially supply a scanning signal, i.e., gate high voltage signal VGH, to the gate lines 20 in response to input control signals. The gate driver ICs 16A to 16D supply a gate low voltage signal VGL to the gate lines in the remaining period except for a period when the gate high voltage signal VGH is supplied.
The signal line group 26 generally includes the following: signal lines that supply DC voltage signals like the gate high voltage signal VGH; the gate low voltage signal VGL; a common voltage signal Vcom; a ground voltage signal GND and a power supply voltage signal VCC that are supplied from a power supply; and gate control signals like a gate start pulse GSP, a gate shift clock signal GSC and a gate output enable signal GOE, which are supplied from a timing controller.
The signal line group 26 of the related art liquid crystal display device is formed in a minute parallel pattern in a very limited narrow space, such as the pad area, which is located at the outer area of the picture display part 21. The signal line group 26 is formed of the same gate metal layer as the gate lines 20. The gate metal is generally a metal that has a relatively high specific resistance 0.046, like AlNd. In this way, the signal line group 26 is formed in a minute pattern in a limited area and of a gate metal which has the relatively high specific resistance. Accordingly, the signal line group 26 includes a relatively high line resistance component X in comparison with the signal lines formed of a copper thin film in the existing gate PCB. Further, the ACF (not shown) for connecting the signal line group 26 to the gate drive signal transmission line group 28 includes a designated connection resistance component Y. In addition, the gate driver signal transmission line group 28 formed on a chip-on-film (COF), or the gate TCP 14A to 14D, include a designated line resistance component Z. These resistance components have a difference as much as X+2Y+2Z between the adjacent ICs. The resistance components cause line resistance to increase with increasing distance from the data PCB 12, thereby attenuating the signal supplied through the signal line group 26. Especially, the common voltage Vcom signal which is the standard of the gate drive signals is distorted by such a resistance, thereby deteriorating the quality of a picture which is displayed in the picture display part 21.
The signal line group 26 has line resistances (a, b, c, d) proportional to its line length, and is connected in series through the first and fourth gate TCPs 14A to 14D. The common voltage Vcom supplied to each gate driver IC 16A to 16D is changed by the line resistances (a, b, c, d) of the signal line group 26. Accordingly, the first to fourth common voltages VCOM1 to VCOM4 have a relationship such that VCOM1>VCOM2>VCOM3>VCOM4. Accordingly, a difference in brightness occurs between horizontal line blocks A to D, which are respectively connected to the gate driver ICs 16A to 16D. The brightness difference of the horizontal line block A to D is shown in a horizontal line 32 phenomenon to make a screen appear to be divided, thereby resulting in a cross-talk phenomenon caused by the resistance between lines as well as a picture quality deterioration.
FIG. 2 illustrates a vertical stripe pattern, which is a test pattern whereby the distortion of the common voltage Vcom is most intensely generated. Herein, an equivalent circuit between a panel and a drive circuit can be expressed as illustrated in FIG. 3.
Referring to FIG. 3, the related art cross-talk phenomenon results from an alternating current Iac, which is imparted to the resistor R_ITO of the common electrode by energy that is stored in capacitors Cb and Cg, which are between a black pixel V_B and a gray pixel V_G. The alternating current Iac forms a path which is connected to a third node Vc and a gamma resistor R_gamma through a pad resistor R_pad that makes the driver IC in contact with the panel. A horizontal cross-talk is generated in a bordering part of a black bar due to a voltage coupling resulting from a difference between the voltage of the common electrode of a second node Vb and a gamma voltage of the third node Vc.